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MII PHY Registers
2-22
to NetSio. Then the clock is cycled for each bit. The loop effectively cycles five
times.
// Send the register number MSB first
// Send the device number Internal=31(0x1f),
External=0(0x00)
for (i = 0x10;i;i >>= 1)
{
if (i&addr)
b |= MDATA;
else
b &= ~MDATA;
outp(diodata,b);
//togLH
b &= ~MCLK; outp(diodata,b);
b |= MCLK; outp(diodata,b);
}
// 802.3u specifies an idle bit time after the register
// address is sent. This and the following zero bit are
// designated as ”Turn–around” cycles.
b &= ~MTXEN; outp(diodata,b);
To get an idle bit, turn off the data driver, then cycle the clock.
//togLH
b &= ~MCLK; outp(diodata,b); //end turn around cycle
b |= MCLK; outp(diodata,b); //this should clock “0”
ackn bit out
b &= ~MCLK; outp(diodata,b); //take clock low wait
for data valid