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10Base-T PHY Registers
A-41
Register Definitions
Table A–19. PHY Generic Control Register Bits (Continued)
Bit Name Function
10 ISOLATE Isolate: When this bit is set (default), the PHY electrically isolates its data paths from the
MII. In this state, it does not respond to the MTXD0–3, MTXEN, and MTXER pin inputs,
and presents a high impedance on its MTCLK, MRCLK, MRXDV, MRXER, MRXD0–3,
and MCOL pin outputs. It, however, still responds to management frames on the MDIO
and MDC pins. Due the the embedded nature of the PHY, the isolate function has no
visible effect on the MII pin interface.
9 AUTORSRT Restart autonegotiation: The autonegotiation process is restarted by setting this bit to
1. This bit is self-clearing, and the PHY returns a value of 1 in this bit until the autonegoti-
ation process is initiated.
8 DUPLEX Duplex mode: Setting this bit to a 1 configures the PHY for full-duplex 10Base-T opera-
tion, whereas setting this bit to 0 (default) configures the PHY for half-duplex operation.
In AUI mode, the PHY is capable of full-duplex operation. The mode is determined by
the external device to which the PHY is interfaced, rather than this bit (which has no ef-
fect on PHY operation).
7 COLTEST Collision test mode: Setting this bit to 1 causes the PHY to assert the collision sense sig-
nal MCOL whenever the transmit enable MTXEN pin is asserted.
6–0
Reserved Read as 0