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Prioritizing Adapter Interrupts
4-5
Interrupt Handling
4.2 Prioritizing Adapter Interrupts
All (non-PCI) adapter interrupts are governed by the interrupt pacing timer.
The interrupt pacing timer is started whenever the HOST_CMD register Ack
bit is written as a 1. When this timer expires and if any interrupt sources are
active, a PCI interrupt is asserted. When the host reads the HOST_INT regis-
ter, the value it reads indicates the highest priority interrupt that is active at that
time.
Interrupts are prioritized in the following order:
Adapter check interrupts cause an internal ThunderLAN reset, clearing all
other interrupt sources. Adapter check interrupts can only be cleared by
a PCI hardware (PRST#) or software (Ad_Rst) reset.
Network status interrupts
Statistics interrupts
List interrupts, which service transmit and receive interrupts in a round-
robin fashion.
Receive end of frame (EOF) interrupts have higher priority than re-
ceive end of channel (EOC) interrupts (an Rx EOC cannot occur until
all EOFs have been acknowledged).
Transmit interrupts are prioritized in channel order; channel 0 has low-
est priority. Transmit EOF interrupts have higher priority than transmit
EOC interrupts (a Tx EOC cannot occur until all EOFs have been ac-
knowledged).