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Adapter Internal Registers
A-24
Table A–8. Network Command Register Bits (Continued)
Bit Name Function
0 TXPACE Transmit pacing (CSMA/CD): This bit allows pacing of transmitted CSMA/CD frames to
improve network utilization of network file servers. When this bit is set, the pacing algo-
rithm is enabled. When this bit is cleared, the pacing algorithm is disabled.
The pacing algorithm automatically delays new adapter frame transmissions in conten-
tion situations. If a transmitted frame either collides with another frame or has to defer
to another transmission, a pacing delay of four interframe gaps (4*96 bit-times) is in-
serted between new frame transmissions. This pacing delay continues to be inserted
until 31 sequential frames are transmitted without collision or deference.
A.3.2 Network Serial I/O Register–NetSio @ 0x00 (DIO)
This register shares control of the external EEPROM interface with the PCI
NVRAM register. Control of the EEPROM interface swaps between these two
control registers on a most-recently-written basis. Whenever the PCI NVRAM
register is written to, it takes control of the EEPROM interface pins. Whenever
the DIO_DATA register is written to, the NetSio register takes control of the
EEPROM interface pins. On reset (software or hardware), control of the inter-
face is given to the PCI NVRAM register. All bits in this register are set to 0 on
an Ad_Rst or when PRST# is asserted.
89101112131415
MDATAMTXENMCLKNMRSTEDATAETXENECLOKMINTEN
Byte 1
Table A–9. Network Serial I/O Register Bits
Bit Name Function
15 MINTEN MII Interrupt enable: When this bit is set to 1, the MIRQ interrupt bit is set if the MDIO
pin is asserted low.
14 ECLOK EEPROM SIO clock: This bit controls the state of the EDCLK pin. When this bit is set
to 1, EDCLK is asserted. When this bit is set to 0, EDCLK is deasserted.
This bit is also used to determine the state of the EEPROM interface. If the EEPROM
port is disabled, this bit is always read as 0, even if a value of 1 is written to the bit.
ThunderLAN detects that the EEPROM port is disabled by sensing the state of the
EDCLK pin during reset. If the EDCLK pin is read as 0 during reset (due to an external
pulldown resistor), then the EEPROM interface is disabled and no attempt is made to
read configuration information.
13
ETXEN EEPROM SIO transmit enable: This bit controls the direction of the EDIO pin. When this
bit is set to 1, EDIO is driven with the value in the EDATA bit. When this bit is set to 0,
the EDATA bit is loaded with the value on the EDIO pin.