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10Base-T PHY Registers
A-42
A.4.2 PHY Generic Status Register–GEN_sts @ 0x1
1JABBERLINK1RFLTAUTOCOMPLT11000
Byte 0Byte 1
Reserved
0123456789101112131415
Table A–20. PHY Generic Status Register Bits
Bit Name Function
15 0 100Base-T4 capable: Not supported
14 0 100Base-Tx full-duplex capable: Not supported
13 0 100Base-Tx half-duplex capable: Not supported
12 1 10Base-T full-duplex capable: This bit is hardwired to 1 to indicate that 10Base-T full
duplex is supported.
11 1 10Base-T half-duplex capable: This bit is hardwired to 1 to indicate 10Base-T half du-
plex is supported.
10–6 Reserved Read as 0
5 AUTOCMPLT Autoconfiguration complete: When this bit is set, it indicates that the autonegotiation
process has finished or was not enabled. If autonegotiation is enabled, this bit also indi-
cates that the contents of registers AN_adv, AN_lpa and AN_exp are valid. This bit is
0 only during an actual negotiation process.
4 RFLT Remote fault: This bit mirrors the LPRFLT bit received in the most recent autonegotiation
link code word. When set to 1, this bit indicates that the link partner is in a fault condition.
3 1 Autonegotiation ability: The PHY supports autonegotiation.
2
LINK Link status: When this bit is read as 1, it indicates that the PHY has determined that a
valid 10Base-T link has been established. When read as 0, it indicates that the link is
not valid. A link invalid state is latched (held) until the register is read. This bit has no
meaning if the AUI interface is selected.
The PHY implements the standard 10Base-T link integrity test state machine. Link
pulses are expected to be seen every 8–24 ms to maintain a good link. If no link pulses
are seen for over 100 ms, the link-fail state is entered and this bit is cleared. If AUTOENB
is not set, the bit is set again after seven consecutive, correctly timed link pulses are re-
ceived. If AUTOENB is set, the link fail causes the autonegotiation process to restart.