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Adapter Host Registers
A-13
Register Definitions
Table A–5. Host
_
CMD Register Bits (Continued)
Bit FunctionName
30 Stop Channel stop: This command bit only affects the network channels.
if R/T = 0 (Tx Stop):
Writing a 1 to this bit stops frame transmission on all transmit channels immediately.
All transmit FIFO control logic and the network transmission state machines are placed
in a reset state as soon as any ongoing PCI bus transfers are complete (end of current
data fragment, list, or CSTAT DMA).
The TXSTOP
2
bit in the NetSts register is set to indicate that the transmitter has
been halted.
If a STOP is requested during the completion of the DMA of a transmit frame, that
frame’s interrupts are posted as normal. If that frame was in the last list on the chan-
nel, then an EOC interrupt is posted as normal.
if R/T = 1 (Rx Stop):
Writing a 1 to this bit stops frame reception on the receive channels immediately. All
receive FIFO control logic and the network reception state machines are placed in a
reset state as soon as any ongoing PCI bus transfers are complete (end of current data
fragment, list, or CSTAT DMA).
The RXSTOP
3
bit in the NetSts register is set to indicate that the receiver has been
halted. While the receiver is stopped, no network Rx statistics are gathered, as the
Rx state machines are in reset.
If a STOP is requested during the completion of the DMA of a transfer frame, that
frame’s interrupts are posted as normal. If that frame was in the last list on the chan-
nel, then an EOC interrupt is posted as normal.
Writing a 0 to this bit has no effect. This bit is always read as 0.
2) The TXSTOP bit is not set if both transmit channels are already idle. The transmitter will, however, be reset.
Because of this, the host must check for EOC or STOP interrupts, in case the transmitter EOCed just as the
STOP command was issued. This window is not desirable, and should be fixed on PG2.0
3) The RXSTOP bit is not set if the receive channel is already idle. The receive is, however, reset. Because
of this, the host must check for EOC or STOP interrupts, in case the receiver EOCed just as the STOP com-
mand was issued. This is not desirable and should be fixed at PG 2.0