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PCI Interface
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1.3 PCI Interface
The PCI local bus is a high-performance, 32- or 64-bit bus with multiplexed ad-
dress and data lines. The bus is designed to be a medium between highly inte-
grated peripheral controller components such as ThunderLAN, add-in boards,
and processor/memory systems.
1.3.1 PCI Cycles
ThunderLAN executes the following cycles when it acts as the PCI bus master.
The hexadecimal number shown is the bus command encoded in the PC/
BE[3::0]# signals.
0x7h–memory write
0xCh–memory read multiple
0xEh–memory read line
ThunderLAN responds to the following PCI cycles when acting in slave mode
on the PCI bus:
0x2h–I/O read
0x3h–I/O write
0x6h–memory read
0x7h–memory write
0xAh–configuration read
0xBh–configuration write
0xCh–memory read multiple
0xEh–memory read line
0xFh–memory write and invalidate
Future versions of ThunderLAN may not be limited to these PCI cycles. Texas
Instruments reserves the right to add or delete any cycles to the ThunderLAN
PCI controller. When designing a system, ensure that the attached interface
to ThunderLAN is fully compliant with the
PCI Local Bus Specification
.