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10Base-T PHY Registers
A-49
Register Definitions
A.4.8 ThunderLAN PHY Control Register–TLPHY_ctl @ 0x11
TINTINTENNFEWMTESTSQEENAUISELSWAPOLIGLINK Reserved
Byte 0Byte 1
01234567
89101112131415
Table A–24. ThunderLAN PHY Control Register Bits
Bit Name Function
15 IGLINK Ignore link: When this bit is set to 0, the 10Base-T PHY expects to receive link pulses
from the link partner (hub, switch, etc.), and sets the LINK bit in the GEN_sts register
to 0 if they are not present. When this bit is set to 1, the internal link integrity test state
machine is forced to stay in the link-good state, even when no link pulses are received.
The LINK bit is set to 1.
14 SWAPOL Swap polarity: Writing a 1 to this bit causes the PHY to reverse the polarity of the
10Base-T receiver input pair. This is used to compensate for a cable in which the receive
pair has been incorrectly wired.
13 AUISEL AUI select: Writing a 1 to this bit causes the PHY to use the AUI network interface; writ-
ing 0 (default) causes the PHY to use the 10Base-T network interface. The transmitters
and receivers on the PHY are multiplexed between AUI and 10Base-T, so both cannot
operate simultaneously.
12 SQEEN SQE (signal quality error) enable: Writing a 1 to this bit causes the 10Base-T PHY to
perform the SQE test function at the end of packet transmission. The SQE function is
only performed in 10Base-T mode.
The SQE test provides an internal simulated collision to test the collision detect circuitry.
It asserts the MCOL bit between 600–1600 ns after the last positive edge of a frame
is transmitted, with the collision lasting between 500 and 1500 ns.
11 MTEST Manufacturing test: When this bit is set to a 1, the PHY is placed into manufacturing test
mode. Manufacturing test mode is reserved for Texas Instruments manufacturing test
only. Operation of the PHY and this register is undefined when this bit is set.
10–3 Reserved Read and write as 0
2
NFEW Not far end wrap: This bit only has meaning when the LOOPBK bit of the GEN_ctl is a
1. Writing a 1 to this bit causes the PHY to wrap the Tx data to the Rx data at the MII.
Writing a 0 to this bit causes the PMI to wrap the Tx data to the Rx data at the furthest
point possible. When NFEW is set to a 1, the preamble wraps without degradation; when
it is set to a 0, the PHY needs only to wrap back the start of frame delimiter (SFD).