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Register Addresses
2-3
ThunderLAN Registers
and PCI configuration registers to make control of the system possible through
the one PCI interface.
An EEPROM, required by the PCI, can be written to at manufacture time
through the PCI_NVRAM register, which is located in the host register space.
The EEPROM can also be accessed through the NetSio register which is lo-
cated in the internal/DIO register space. Control registers on the PHY side of
the MII management interface can be similarly written and read through the
NetSio register.
A BIOS ROM can be enabled via the BRE bit in the PCI BIOS ROM base ad-
dress register, and its chip selected address dynamically assigned via a base
register in the configuration space. The BRE bit points to a valid address in the
ROM address space which causes two byte-address strobe cycles (EALE,
EXLE) and a read before the PCI cycle is completed.