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2.4 System board Troubleshooting 2 Troubleshooting
Satellite R20/TECRA M7 Maintenance Manual (960-572) [CONFIDENTIAL] 2-23
Table 2-4 Debug port (Boot mode) error status (3/10)
D port status Inspection items Details
Initialization of MCHM
Initialization of ICH7M.D30.Func0
Initialization of ICH7M.D31.Func0
Initialization of ICH7M.D31.Func1/2
Initialization of USB controller
Initialization of ICH7M.D31.Func3
Initialization of H/W (before DRAM
recognition)
Initialization of TI controller
(F100h)
Initialization of PIT channel 1
(Setting the refresh interval to “30μs”)
Checking DRAM type and size
(at cold boot)
When unsupported memory is connected,
the system beeps and halts
When DRAM size = 0, halts
F101h
Testing the stack area of SM-RAM When it can not be used as stack area,
halts
Configuring cache memory
Permission of L1/L2 cache
memory
Checking the access of a CMOS
(Only in Cold Boot)
When error is detected, halts
Examining the battery level of
CMOS
Checksum check of CMOS
Initializing data in CMOS (1)
Setting up of IRT status (Setting of boot status and IRT busy flag,
The rest bits are set to 0)
F102h
Storing the size of DRAM
F103h Branch of resuming (only in Cold
Boot)
When a CMOS error is detected, it does
not resume
If “resume status code” is not set, no
resume occurs