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NetXtreme II User Guide
January 2010
Broadcom Corporation
Page 232 Diagnostic Test Descriptions Document ENGSRVT52-CDUM100-R
DIAGNOSTIC TEST DESCRIPTIONS
The diagnostic tests are divided into four groups: Basic Functional Tests (Group A), Memory Tests (Group B), Block Tests
(Group C), and Ethernet Traffic Tests (Group D). The diagnostic tests are listed and described in Table 3.
Table 3: Diagnostic Tests
Test
Description
Number Name
Group A: Basic Functional Tests
A1 Register Verifies that registers accessible through the PCI/PCI-E interface implement the
expected read-only or read/write attributes by attempting to modify those
registers.
A2 PCI Configuration Checks the functionality of the PCI Base Address Register (BAR) by varying the
amount of memory requested by the BAR and verifying that the BAR actually
requests the correct amount of memory (without actually mapping the BAR into
system memory). Refer to PCI or PCI-E specifications for details on the BAR and
its addressing space.
A3 Interrupt Generates a PCI interrupt and verifies that the system receives the interrupt and
invokes the correct ISR. A negative test is also performed to verify that a masked
interrupt does not invoke the ISR.
A5 MSI Verifies that a Message Signaled Interrupt (MSI) causes an MSI message to be
DMA’d to host memory. A negative test is also performed to verify that when an
MSI is masked, it does not write an MSI message to host memory.
A6 Memory BIST Invokes the internal chip Built-In Self Test (BIST) command to test internal
memory.
Group B: Memory Tests
B1 TXP Scratchpad The Group B tests verify all memory blocks of the Broadcom NetXtreme II
adapter by writing various data patterns (0x55aa55aa, 0xaa55aa55, walking
zeroes, walking ones, address, etc.) to each memory location, reading back the
data, and then comparing it to the value written. The fixed data patterns are used
to ensure that no memory bit is stuck high or low, while the walking zeroes/ones
and address tests are used to ensure that memory writes do not corrupt adjacent
memory locations.
B2 TPAT Scratchpad
B3 RXP Scratchpad
B4 COM Scratchpad
B5 CP Scratchpad
B6 MCP Scratchpad
B7 TAS Header Buffer
B8 TAS Payload Buffer
B9 RBUF via GRC
B10 RBUF via Indirect
Access
B11 RBUF Cluster List
B12 TSCH List
B13 CSCH List
B14 RV2P Scratchpads
B15 TBDC Memory
B16 RBDC Memory
B17 CTX Page Table
B18 CTX Memory
Group C: Block Tests