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Technical Reference Guide
Compaq Deskpro EN Series of Personal Computers
Desktop and Minitower Form Factors
Third Edition–- September1998
viii
LIST OF FIGURES
F
IGURE
2–1. C
OMPAQ
D
ESKPRO
EN P
ERSONAL
C
OMPUTER WITH
M
ONITOR
........................................... 2-1
F
IGURE
2–2. C
ABINET
L
AYOUTS
, F
RONT
V
IEW
...................................................................................... 2-4
F
IGURE
2–3. C
ABINET
L
AYOUTS
, R
EAR
V
IEW
........................................................................................ 2-5
F
IGURE
2–4. D
ESKTOP
C
HASSIS
L
AYOUT
, T
OP
V
IEW
.............................................................................. 2-6
F
IGURE
2–5. M
INITOWER
C
HASSIS
L
AYOUT
, L
EFT
S
IDE
V
IEW
................................................................ 2-7
F
IGURE
2–6. S
YSTEM
B
OARD
C
ONNECTOR AND
S
WITCH
L
OCATIONS
...................................................... 2-8
F
IGURE
2–7. B
ACKLPANE
B
OARD
C
ONNECTOR
, H
EADER
,
AND
S
WITCH
L
OCATIONS
................................ 2-9
F
IGURE
2–8. S
YSTEM
A
RCHITECTURE
, B
LOCK DIAGRAM
...................................................................... 2-11
F
IGURE
2–9. P
ROCESSOR
P
ACKAGE
C
OMPARISON
................................................................................ 2-12
F
IGURE
3–1. P
ROCESSOR
/M
EMORY
S
UBSYSTEM
A
RCHITECTURE
............................................................ 3-2
F
IGURE
3–2. P
ENTIUM
II P
ROCESSOR
I
NTERNAL
A
RCHITECTURE
............................................................ 3-3
F
IGURE
3–3. C
ELERON
P
ROCESSOR
I
NTERNAL
A
RCHITECTURE
............................................................... 3-4
F
IGURE
3–4. S
YSTEM
M
EMORY
M
AP
..................................................................................................... 3-8
F
IGURE
4–1. PCI B
US
D
EVICES AND
F
UNCTIONS
.................................................................................... 4-2
F
IGURE
4–2. PCI B
US
C
ONNECTOR
(32-B
IT
T
YPE
)................................................................................. 4-3
F
IGURE
4–3. T
YPE
0 C
ONFIGURATION
C
YCLE
........................................................................................ 4-6
F
IGURE
4–4. PCI C
ONFIGURATION
S
PACE
M
AP
...................................................................................... 4-7
F
IGURE
4–5. AGP 1X D
ATA
T
RANSFER
(P
EAK
T
RANSFER
R
ATE
: 266 MB/
S
) ........................................ 4-12
F
IGURE
4–6. AGP 2X D
ATA
T
RANSFER
(P
EAK
T
RANSFER
R
ATE
: 532 MB/
S
) ........................................ 4-13
F
IGURE
4–7. AGP B
US
C
ONNECTOR
................................................................................................... 4-15
F
IGURE
4–8. ISA B
US
B
LOCK
D
IAGRAM
............................................................................................. 4-16
F
IGURE
4–9. ISA E
XPANSION
C
ONNECTOR
.......................................................................................... 4-17
F
IGURE
4–10. M
ASKABLE
I
NTERRUPT
P
ROCESSING
, B
LOCK
D
IAGRAM
.................................................. 4-23
F
IGURE
4–11. C
ONFIGURATION
M
EMORY
M
AP
.................................................................................... 4-29
F
IGURE
5–1. 40-P
IN
IDE C
ONNECTOR
. ................................................................................................. 5-8
F
IGURE
5–2. 34-P
IN
D
ISKETTE
D
RIVE
C
ONNECTOR
.............................................................................. 5-13
F
IGURE
5–3. S
ERIAL
I
NTERFACES
B
LOCK
D
IAGRAM
............................................................................. 5-14
F
IGURE
5–4. S
ERIAL
I
NTERFACE
C
ONNECTOR
(M
ALE
DB-9
AS VIEWED FROM REAR OF CHASSIS
) ........... 5-14
F
IGURE
5–5. P
ARALLEL
I
NTERFACE
C
ONNECTOR
(F
EMALE
DB-25
AS VIEWED FROM REAR OF CHASSIS
).. 5-26
F
IGURE
5–6. 8042-T
O
-K
EYBOARD
T
RANSMISSION OF
C
ODE
ED
H
, T
IMING
D
IAGRAM
............................ 5-27
F
IGURE
5–7. K
EYBOARD OR
P
OINTING
D
EVICE
I
NTERFACE
C
ONNECTOR
............................................... 5-33
F
IGURE
5–8. U
NIVERSAL
S
ERIAL
B
US
C
ONNECTOR
(
ONE OF TWO AS VIEWED FROM REAR OF CHASSIS
)..... 5-35
F
IGURE
6–1. A
UDIO
S
UBSYSTEM
B
LOCK
D
IAGRAM
................................................................................ 6-3
F
IGURE
6–2. A
NALOG
S
IGNAL
S
AMPLING
/Q
UANTIZING
.......................................................................... 6-4
F
IGURE
6–3. DAC O
PERATION
............................................................................................................. 6-5
F
IGURE
6–4. A
UDIO
S
UBSYSTEM
-
TO
-ISA B
US
PCM A
UDIO
D
ATA
F
ORMATS
/ B
YTE
O
RDERING
.............. 6-6
F
IGURE
6–5. FM S
YNTHESIS
P
ATCH
...................................................................................................... 6-7
F
IGURE
6–6. A
UDIO
C
AR
-
TO
-ISA B
US
FM A
UDIO
D
ATA
F
ORMAT
.......................................................... 6-7
F
IGURE
7–1. P
OWER
D
ISTRIBUTION AND
C
ONTROL
, B
LOCK
D
IAGRAM
.................................................... 7-1
F
IGURE
7–2. P
OWER
C
ABLE
D
IAGRAM
.................................................................................................. 7-5
F
IGURE
7–3. L
OW
V
OLTAGE
S
UPPLY
, B
LOCK
D
IAGRAM
......................................................................... 7-6
F
IGURE
7–4. S
IGNAL
D
ISTRIBUTION
D
IAGRAM
....................................................................................... 7-7
F
IGURE
7–5. B
ACKPLANE
H
EADER
P
INOUTS
........................................................................................... 7-8