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Technical Reference Guide
Compaq Deskpro EN Series of Personal Computers
Desktop and Minitower Form Factors
Third Edition–- September1998
iv
CHAPTER 4 SYSTEM SUPPORT.........................................................................................................
4.1 INTRODUCTION.................................................................................................................. 4-1
4.2 PCI BUS OVERVIEW........................................................................................................... 4-2
4.2.1 PCI CONNECTOR......................................................................................................... 4-3
4.2.2 PCI BUS MASTER ARBITRATION.............................................................................. 4-4
4.2.3 PCI BUS TRANSACTIONS........................................................................................... 4-5
4.2.4 OPTION ROM MAPPING ............................................................................................. 4-8
4.2.5 PCI INTERRUPT MAPPING ......................................................................................... 4-9
4.2.6 PCI POWER MANAGEMENT SUPPORT.....................................................................4-9
4.2.7 PCI CONFIGURATION............................................................................................... 4-10
4.3 AGP BUS OVERVIEW ....................................................................................................... 4-11
4.3.1 BUS TRANSACTIONS................................................................................................ 4-11
4.3.2 AGP CONFIGURATION ............................................................................................. 4-14
4.3.3 AGP CONNECTOR..................................................................................................... 4-15
4.4 ISA BUS OVERVIEW......................................................................................................... 4-16
4.4.1 ISA CONNECTOR ...................................................................................................... 4-17
4.4.2 ISA BUS TRANSACTIONS......................................................................................... 4-18
4.4.3 DIRECT MEMORY ACCESS...................................................................................... 4-20
4.4.4 INTERRUPTS.............................................................................................................. 4-23
4.4.5 INTERVAL TIMER.....................................................................................................4-27
4.4.6 ISA CONFIGURATION............................................................................................... 4-27
4.5 SYSTEM CLOCK DISTRIBUTION.................................................................................... 4-28
4.6 REAL-TIME CLOCK AND CONFIGURATION MEMORY............................................... 4-29
4.7 I/O MAP AND REGISTER ACCESSING............................................................................ 4-46
4.7.1 SYSTEM I/O MAP ...................................................................................................... 4-46
4.7.2 GPIO UTILIZATION................................................................................................... 4-47
4.8 SYSTEM MANAGEMENT SUPPORT ............................................................................... 4-51
4.8.1 FLASH ROM WRITE PROTECT ................................................................................ 4-52
4.8.2 PASSWORD PROTECTION........................................................................................ 4-52
4.8.3 I/O SECURITY ............................................................................................................ 4-53
4.8.4 USER SECURITY........................................................................................................ 4-53
4.8.5 TEMPERATURE SENSING........................................................................................ 4-54
4.8.6 SMART COVER LOCK............................................................................................... 4-55
4.8.7 SMART COVER REMOVAL SENSOR....................................................................... 4-55
4.8.8 POWER MANAGEMENT........................................................................................... 4-56
CHAPTER 5 INPUT/OUTPUT INTERFACES.....................................................................................
5.1 INTRODUCTION.................................................................................................................. 5-1
5.2 ENHANCED IDE INTERFACE ............................................................................................ 5-1
5.2.1 IDE PROGRAMMING................................................................................................... 5-1
5.2.2 IDE CONNECTOR ........................................................................................................5-8
5.3 DISKETTE DRIVE INTERFACE.......................................................................................... 5-9
5.3.1 DISKETTE DRIVE PROGRAMMING ........................................................................ 5-10
5.3.2 DISKETTE DRIVE CONNECTOR.............................................................................. 5-13
5.4 SERIAL INTERFACES....................................................................................................... 5-14
5.4.1 RS-232 INTERFACE ................................................................................................... 5-14
5.4.2 SERIAL INTERFACE PROGRAMMING.................................................................... 5-15