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Chapter 8 BIOS ROM
Compaq Deskpro EN Series of Personal Computers
Desktop and Minitower Form Factors
Third Edition - September 1998
8-2
8.2 BOOT/RESET FUNCTIONS
The system supports new system boot functions to support remote ROM flashing and PC97
requirements. This system also supports the EL Torito specification for bootable CDs.
8.2.1 BOOT BLOCK
This system includes 24 KB of write-protected boot block ROM that provides a way to recover
from a failed remote flashing of the system BIOS ROM. Early during the boot process, the boot
block code checks the system ROM. If validated, the system BIOS continues the boot sequence.
If the system ROM fails the check, the boot block code provides the minimum amount of support
necessary to allow booting the system from the diskette drive (bypassing the security measures)
re-flashing the system ROM with a ROMPAQ diskette. Since video is not available during the
initial boot sequence the boot block routine uses the keyboard LEDs to communicate status as
follows:
Num Lock Caps Lock
Scroll Lock Meaning
Off On Off Administrator password required.
On Off Off Boot failed. Reset required for retry.
Off Off On Flash failed (set by ROMPAQ).
On On On Flash complete (set by ROMPAQ).
8.2.2 QUICKBOOT
The QuickBoot mode (programmable through the INT 15, AX=E845h call) skips certain portions
of the POST (such as the memory count) during the boot process
unless
the hood has been
detected as being removed. The QuickBoot mode is programmable as to be invoked always, never
(default) or every x-number of days.
8.2.3 SILENTBOOT
When in the SilentBoot mode, the boot process skips certain audio and visual aspects of POST
(such as the speed beeps and screen messages). Error messages are still displayed. The
QuickBoot mode is programmable by the Setup utility (through the INT 15, AX=E845h call) as
to either TERSE (default) or VERBOSE mode.
8.2.4 RESET
There are two types of system resets: hard and soft. A hard reset is traditionally generated after
power-up and produced by the circuitry generating the PWRGOOD signal. The 82371 south
bridge, however, allows software to generate a hard reset. This is accomplished by first writing a
one (1) to bit <1> of I/O port 0CF9h. A one is then written to bit <2> of 0CF9h. This causes the
82371 to create a hard reset by asserting CPURST#, PCIRST#, and RSTDRV for at least 1 ms.
After the reset the 82371 automatically clears bit <2> of 0CF9h.