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Technical Reference Guide
Compaq Personal Computers
Change –- April 1998
C-3
C.2.1 TRANSMISSIONS TO THE SYSTEM
The keyboard processor sends two main types of data to the system; commands (or responses to
system commands) and keystroke scan codes. Before the keyboard sends data to the system
(specifically, to the 8042-type logic within the system), the keyboard verifies the clock and data
lines to the system. If the clock signal is low (0), the keyboard recognizes the inhibited state and
loads the data into a buffer. Once the inhibited state is removed, the data is sent to the system.
Keyboard-to-system transfers consist of 11 bits as shown in Figure C-2.
Parameter Minimum
Maximum
Tcy (Cycle Time) 60 us 80 us
Tcl (Clock Low) 30 us 35 us
Tch (clock High) 30 us 45 us
Th (Data Hold) 45 us 62 us
Ts (Data Setup) 8 us 14 us
Figure C–2.
Keyboard-To-System Transmission of Code 58h, Timing Diagram
The system can halt keyboard transmission by setting the clock signal low. The keyboard checks
the clock line every 60 us to verify the signal state. If a low is detected, the keyboard will finish
the current transmission
if
the rising edge of the clock pulse for the parity bit has not occurred.
The enhanced keyboard has three operating modes:
♦
Mode 1 - PC-XT compatible
♦
Mode 2 - PC-AT compatible (default)
♦
Mode 3 - Select mode (keys are programmable as to make-only, break-only, typematic)
Modes can be selected by the user or set by the system. Mode 2 is the default mode. Each mode
produces a different set of scan codes. When a key is pressed, the keyboard processor sends that
key’s make code to the 8042 logic of the system unit. The When the key is released, a release
code is transmitted as well (except for the Pause key, which produces only a make code). The
8042-type logic of the system unit responds to scan code reception by asserting IRQ1, which is
processed by the interrupt logic and serviced by the CPU with an interrupt service routine. The
service routine takes the appropriate action based on which key was pressed.
Start
Bit
D0
(LSb)
D1 D2 D3 D4 D5 D6
D7
(MSb)
Parity
Stop
Bit
00001111100
Data
Clock
Ts
Tcl TchTcy
Th