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Document 38-08035 Rev. *K Page 71 of 83
1
Figure 28-2. GPIO Timing Diagram
Figure 28-1. Clock Timing
Figure 28-3. USB Data Signal Timing
CLOCK
T
CYC
T
CL
T
CH
10%
T
R_GPIO
T
F_GPIO
GPIO Pin Output
Voltage
90%
90%
10%
90%
10%
D
−
D
+
T
R
T
F
V
crs
V
oh
V
ol
Figure 28-4. Receiver Jitter Tolerance
Differential
Data Lines
Paired
Transitions
N * T
PERIOD
+ T
JR2
T
PERIOD
Consecutive
Transitions
N * T
PERIOD
+ T
JR1
T
JR
T
JR1
T
JR2
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