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S1F76640 Series
2–62 EPSON S1F70000 Series
Technical Manual
Configuration Example of Voltage Stabilized Output (VREG) Electronic Volume Circuit
Figure 8.9
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
RI
(74HC4051)
13
14
15
12
1
5
2
4
11
10
9
6
16
78
3
CTRL0
XPOF
(V
DD
/V
SS
)
CTRL1
V
SS
or V
O
V
SS
or V
O
Negative voltage input
Voltage stabilized output (V
REG
)
Positive voltage input
CTRL2
V
O
CAP3+
CAP2+
CAP2–
CAP1+
CAP1–
V
DD
RV
V
REG
TC1
TC2
P
OFF
V
SS
OSC1
OSC2
+
–
+
–
+
–
+
–
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
V
CC
V
EE
V
SS
COM
INH
A
B
C