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Using the Computer Interface
General Information (RS-232 and IEEE-488)
4
4-19
Table 4-4. Status Byte Register
Bit Name Description
0 IEB Instrument Event Bit. When any bit in the Instrument Event Register is set and
the corresponding mask bit(s) in the Instrument Event Enable register is set,
this Instrument Event Bit in the Status Byte will be set.
When read, the Instrument Event Bit is recomputed based on the new value
from the Instrument Event Register and its mask, the Instrument Event Enable
Register.
1,2,3 not used
4 MAV Message Available
5 ESB Event Status Bit
6 RQS/MSS Request Service/Master Summary Status
7 not used
Event Status and Event Status Enable Registers
The Event Status Register (ESR) records specified events in specific bits. (See Figure 4-
4 and Table 4-5). When a bit in the ESR is set (i.e., 1), the event that corresponds to that
bit has occurred since the register was last read or cleared. For example, if bit 3 (DDE) is
set to 1, a device-dependent error has occurred.
The Event Status Enable Register (ESE) is a mask register that allows the host to enable
or disable (mask) each bit in the ESR. When a bit in the ESE is 1, the corresponding bit
in the ESR is enabled. When any enabled bit in the ESR changes from 0 to 1, the ESB bit
in the Status Byte Register also goes to 1. When the ESR is read (using the *ESR?
query) or cleared (using the *CLS command), the ESB bit in the Status Byte Register
returns to 0.
Status Byte Register
The Status Byte Register (STB) is a binary-encoded register that contains eight bits.
Note that the Service Request Enable Register (SRE) uses bits 1 through 5 and bit 7 to
set bit 6, the request service (RQS) bit, as enabled by the SRE. When the RQS bit is set
true (1), the instrument sets the SRQ line true (1), which generates a service request. The
eight bits of the Status Byte Register (as read by the *STB? query) are described in
Table 4-4.