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Chapter 1. Technical description 9
The CPUs are connected together with a 100 MHz frontside bus, but supply data
at an effective rate of 400 MHz using the “quad-pump” design of the Intel
NetBurst architecture as described in 1.4.1, “Intel Xeon Processor MP” on
page 13. To ensure the processors are optimally used, the x440 has a 32 MB
XceL4 Server Accelerator Cache, comprised of 200 MHz DDR memory. This L4
system cache services all CPUs in an SMP Expansion Module.
Memory used in the x440 is standard 133 MHz ECC SDRAM DIMMs; however,
the 133 MHz DIMMs are run at 100 MHz (for parts availability reasons). With
2 GB DIMMs, up to 32 GB can be installed using all 16 DIMM sockets. The
memory is four-way interleaved so that the memory subsystem can supply data
fast enough to match the throughput of the CPUs. Four-way interleaving means
that DIMMs must be installed in matched fours and in specific DIMM sockets (see
3.1.2, “Memory” on page 65).
The second SMP Expansion Module can be installed when more than four Xeon
MP processors, or two Xeon DP processors, are required. This also enables the
system to have up to 64 GB of RAM, using 2 GB DIMMs. The block diagram with
two SMP Expansion Modules is shown in Figure 1-5 on page 10.
Note: When Xeon DP processors are used, only two CPUs can be installed in
each SMP Expansion Module. The processors are installed in CPU positions
1 and 4. Positions 2 and 3 must hold air baffles to maintain proper air flow.