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BDM-610000049 Rev G Chapter 1: Introduction 3
Enhanced Intel SpeedStep (PX only)
Enhanced Intel® SpeedStep® Technology has revolutionized thermal and power management by giving
application software greater control over the processor’s operating frequency and input voltage. Systems can
easily manage power consumption dynamically. Today’s embedded systems are demanding greater performance
at equivalent levels of power consumption. Legacy hardware support for backplanes, board sizes and thermal
solutions have forced design teams to place greater emphasis on power and thermal budgets. Intel has extended
architectural innovation for saving power by implementing new features such as Enhanced Intel SpeedStep
Technology. Enhanced Intel SpeedStep Technology allows the processor performance and power consumption
levels to be modified while a system is functioning. This is accomplished via application software, which changes
the processor speed and the processor core voltage while the system is operating. A variety of inputs such as
system power source, processor thermal state, or operating system policy are used to determine the proper
operating state.
The software model behind Enhanced Intel SpeedStep Technology has ultimate control over the frequency and
voltage transitions. This software model is a major step forward over previous implementations of Intel
SpeedStep technology. Legacy versions of Intel SpeedStep technology required hardware support through the
chipset. Enhanced Intel SpeedStep Technology has removed the chipset hardware requirement and only requires
the support of the voltage regulator, processor and operating system. Centralization of the control mechanism
and software interface to the processor, and reduced hardware overhead has reduced processor core
unavailability time to 10 μs from the previous generation unavailability of 250 μs.
Thermal Monitor
The Intel ® Thermal Monitor is a feature on the CMX158886 that automatically initiates a SpeedStep transition
or throttles the CPU when the CPU exceeds its thermal limit. The maximum temperature of the processor is
defined as the temperature that the Thermal Monitor is activated. The thermal limit and duty cycle of the
Thermal Monitor cannot be modified.
Error-Correction Codes (Selected Models Only)
The Graphics and Memory Controller Hub (GMCH) may be configured in the BIOS setup to operate in an
Error-Correction-Code (ECC) data integrity mode. ECC mode allows multiple bit error detection and single bit
error correction. The GMCH generate an 8-bit code word for each 64-bit Qword of memory, and performs a full
Qword write at a time so that an 8-bit code is sent with each write. Since the code word covers a full Qword,
writes of less than a Qword require a read-merge-write operation. Consider a Dword write to memory. In this
case, when in ECC mode, GMCH will read the Qword where the addressed Dword will be written, merge in the
new Dword, generate a code covering the new Qword and finally write the entire Qword and code back to
memory. Any correctable (single-bit) errors detected during the initial Qword read are corrected before merging
the new Dword.
Memory with ECC enabled requires additional system memory resources. This will cause the integrated graphics
engine to have less memory bandwidth for access to the graphics frame buffer. Because of this, the display may
flicker at high resolutions when the graphics processor is fully utilized and ECC is enabled. ECC memory is
supported with internal graphics only.
aDIO with Wake-on-aDIO
RTD’s exclusive multiPort™ allows the parallel port to be configured as an Advanced Digital I/O (aDIO™), ECP/
EPP parallel port, or a floppy drive. aDIO™ is 16 digital bits configured as 8 bit-direction programmable and 8-bit
port-direction programmable I/O giving you any combination of inputs and outputs. Match, event, and strobe
interrupt modes mean no more wasting valuable processor time polling digital inputs. Interrupts are generated
when the 8 bit-direction programmable digital inputs match a pattern or on any value change event. Bit masking