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Software Developer’s Manual 87
PCI Local Bus Interface
Following are a few specific rules:
• For descriptor fetches, the burst length is always equal to the multiple of cache line sizes set by
the transmit and receive descriptor fetch threshold fields. (See Section 3.2.4 and Section 3.4.1)
For descriptor writes, the transfer size ranges from 8 bytes to N cache line's worth of data.
Cache line sizes are: 16, 32, 64, and 128 bytes.
• For transmit data fetches, the burst length is generally equal to the block of data being fetched,
in other words, a descriptor's worth of data.
• For receive data writes, the burst size is typically equal to the packet length (rounded up to the
next 8 bytes) or the buffer size, whichever is smaller.
4.3 PCI/PCI-X Command Usage
The Ethernet controller optimizes the use of PCI/PCI-X bus cycles to maximize throughput. The
following sections describe this behavior.
4.3.1 Memory Write Operations
Memory write command usage has been implemented in the Ethernet controller to improve PCI
performance. As noted below, cache line size has a significant impact on the usage of memory
write commands. Specifically, cache line size entries which are unsupported causes hardware to
default to the Memory Write (MW) command for all master write transactions. Also, all writes
default to MW if the Memory Write and Invalidate (MWI) enable bit in the PCI configuration
command register is 0b. MWI is the preferred write command and is used when the circumstances
allow it.
Figure 4-4 depicts a behavioral state-machine representation of the command usage algorithm for
master write operations.
Upon EACH master write access, the hardware evaluates the address alignment and the amount of
data to be transferred. The following guidelines are used for command determination:
• If the address is cache line aligned and there is at least one cache line of data, then hardware
uses the MWI command.
• If the address is aligned but there is not at least one cache line of data, or the address is not
aligned, or if the MWI enable bit is set to 0b, then hardware uses the MW command.
During the burst, regardless of which command was originally issued, the hardware evaluates the
remaining amount of data each time the write burst comes to a cache line boundary, or when the
transaction is terminated due to a target disconnect or latency timer expiration.