Filter
Top Products
Software Developer’s Manual 343
Register Descriptions
Table 13-96. RXERRC Register Bit Description
13.7.5 Missed Packets Count
MPC (04010h; R)
Counts the number of missed packets. Packets are missed when the receive FIFO has insufficient
space to store the incoming packet. This can be caused because of too few buffers allocated, or
because there is insufficient bandwidth on the PCI bus. Events setting this counter cause RXO, the
Receiver Overrun Interrupt, to be set. This register does not increment if receives are not enabled.
These packets are also counted in the Total Packets Received register as well as in Total Octets
Received.
Table 13-97. MPC Register Bit Description
13.7.6 Single Collision Count
SCC (04014h; R)
This register counts the number of times that a successfully transmitted packet encountered a single
collision. This register only increments if transmits are enabled and the Ethernet controller is in
half-duplex mode.
31 0
RXEC
Field Bit(s)
Initial
Value
Description
RXEC 31:0 0b RX error count
31 0
MPC
Field Bit(s)
Initial
Value
Description
MPC 31:0 0b Missed Packets Count