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264 Software Developer’s Manual
Register Descriptions
13.4.7.1.13 PHY Specific Control Register
PSCON (16d; R/W)
Table 13-31. PHY Specific Control Register Bit Description
Field Bit(s)
Description
Mode HW Rst SW Rst
1000BASE-T 10/100BASE-T
Disable Jabber 0
1b = Disable jabber function.
0b = Enable jabber function.
Jabber has effect only in 10BASE-T half
duplex mode.
R/W 0b Retain
Polarity Reversal 1
1b = Polarity Reversal Disabled.
0b = Polarity Reversal Enabled.
If polarity is disabled, then the polarity is
forced to be normal in 10BASE-T.
R/W 0b Retain
SQE Test 2
1b = SQE test enabled.
0b = SQE test disabled.
Jabber has effect only in 10BASE-T half
duplex mode.
R/W 0b Retain
MAC Interface Power
Down
3
1b = Always power up.
0b = Can power down.
This bit determines whether the MAC
interface powers down when register
PHY Control Register bit 11 is used to
power down the Ethernet controller or
when the PHY enters the energy detect
state.
R/W 1b Update
Disable 125CLK
1
Reserved
4
1b = 125CLK Low.
0b = 125CLK Toggling.
Bit 4 = ENA_XC.
This bit is reserved for all Ethernet
controllers except the 82544GC/EI.
Should be set to 0b.
R/W
DIS_
125CLK
1
0b
Update
MDI Crossover Mode 6:5
00b = Manual MDI configuration.
01b = Manual MDI-X configuration.
10b = Reserved.
11b = Enable automatic crossover for all
modes.
82544GC/EI only:
Bit 6 = DIS_125.
Bit 5 = ENA_XC.
R/W 11b Update
Enable Extended
Distance
7
1b = Lower 10BASE-T receive
threshold.
0b = Normal 10BASE-T receive
threshold.
When a cable longer than 100 m is
used, the 10BASE-T receive threshold
must be lowered in order to detect
incoming signals.
R/W 0b Retain