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Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—General Hardware
Design Considerations
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
HDD February 2007
24 Document Number: 305261; Revision: 004
For example, as in this case when booting of a 16-bit flash device, bit 0 and 7 of
Configuration Register 0 must be set as follows:
• Bit 0 = 0.
This can be done by placing an external 4.7-KΩ pull-down resistor to pin
EX_ADDR[0].
• Bit 7 = 0.
This can be done by placing an external 4.7-KΩ pull-down resistor to pin
EX_ADDR[7].
If it is required to change access mode, after the system has booted, and during
normal operation; the Timing and Control Register for Chip Select must be configured
to perform the desired mode access. For a complete description on accomplishing this
refer to the “Expansion Bus” chapter in the Intel
®
IXP45X and Intel
®
IXP46X Product
Line of Network Processors Developer’s Manual.
3.3.5 32-Bit Device Interface
The IXP45X/IXP46X network processors support 32-bit wide data bus devices (32-bit
word mode). For Intel interface cycles, the data lines and control signals can be
connected as shown in Figure 3 on page 25 and Figure 4 on page 26.
When booting a 32-bit flash device, the expansion bus must be configured during reset
to the 32-bit mode (see Configuration Register 0). To accomplish this, boot-strapping is
required in certain address pins of the Expansion bus. For example, as in this case
when booting of a 32-bit flash device, bit 0 and 7 of Configuration Register 0 must be
set as follows:
• Bit 0 = 1.
By default this bit is set high when coming off reset or any time reset is asserted.
• Bit 7 = 1.
By default this bit is set high when coming off reset or any time reset is asserted.
If it is required to change access mode, after the system has booted, and during
normal operation; the Timing and Control Register for Chip Select must be configured
to perform the desired mode access. For a complete description on accomplishing this
refer to the “Expansion Bus” chapter in the Intel
®
IXP45X and Intel
®
IXP46X Product
Line of Network Processors Developer’s Manual.