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IXP45X and Intel
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IXP46X Product Line of Network Processors—Category
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
HDD February 2007
98 Document Number: 305261, Revision: 004
7.2.3 Control Group
The control signal group includes the signals DDRI_CS[1:0] and DDRI_CKE[1:0]. The
following simulations were constructed for the 2 bank x16 device configuration where
each signal would have three receivers.
Table 38 identifies the transmission line lengths for the chip select (CS0) topology
shown in Figure 43 on page 98. These lengths were chosen as realistic goals given the
IXP45X/IXP46X network processors to DDR body to body separation of no more than
500 mils.
Table 38. Control Group Topology Transmission Line Characteristics
Transmission Line Length
TL1 (T
pd
= 175 ps/in) ~ 600 mils
TL2 (T
pd
= 175 ps/in) ~ 50 mils
TL3 (T
pd
= 175 ps/in) ~ 1,100 mils
TL4 (T
pd
= 175 ps/in) ~ 50 mils
TL5, TL6, TL7 (T
pd
= 175 ps/in) ~ 800 mils
TL8, TL9, TL10 (T
pd
= 175 ps/in) ~ 300 mils
Figure 43. DDR Control (CS0) Topology: Two-Bank x16 Devices