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IXP45X and Intel
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IXP46X Product Line of Network Processors—Contents
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
HDD February 2007
6 Document Number: 305261, Revision: 004
44 DDR RAS Simulation Results: Two-Bank x16 Devices ....................................................99
45 DDR Command (MA3) Topology: Two-Bank x16 Devices..............................................101
46 DDR Address Simulation Results: Two-Bank x16 Devices .............................................102
47 DDR Command (RAS) Topology: Two-Bank x16 Devices ..............................................103
48 DDR RAS Simulation Results: Two-Bank x16 Devices ..................................................104
49 DDR RCVENIN/RCVENOUT Topology..........................................................................105
50 DDR RCVENIN/RCVENOUT Simulation Results (Rseries = 0 W) .....................................106
51 DDR RCVENIN/RCVENOUT Simulation Results (Rseries = 60 W)....................................107
Tables
1 List of Acronyms and Abbreviations.............................................................................11
2 Signal Type Definitions..............................................................................................17
3 Soft Fusible Features ................................................................................................18
4 DDR SDRAM Interface Pin Description .........................................................................18
5 Expansion Bus Signal Recommendations......................................................................21
6 Boot/Reset Strapping Configuration ............................................................................22
7 UART Signal Recommendations ..................................................................................29
8 MII NPE A Signal Recommendations............................................................................31
9 MII NPE B Signal Recommendations............................................................................31
10 MII NPE C Signal Recommendations............................................................................32
11 MAC Management Signal Recommendations NPE A,B,C..................................................33
12 SMII Signal Recommendations: NPE A, B, C.................................................................34
13 GPIO Signal Recommendations...................................................................................36
14 I2C Signal Recommendations.....................................................................................37
15 USB Host/Device Signal Recommendations ..................................................................39
16 UTOPIA Signal Recommendations ...............................................................................42
17 High-Speed, Serial Interface 0 ...................................................................................44
18 High-Speed, Serial Interface 1 ...................................................................................45
19 Synchronous Serial Peripheral Port Interface ................................................................47
20 PCI Controller ..........................................................................................................48
21 PCI Host/Option Interface Pin Description ....................................................................51
22 Synchronous Serial Peripheral Port Interface ................................................................54
23 Clock Signals ...........................................................................................................54
24 Power Interface........................................................................................................55
25 PCI Address/Data Routing Guidelines ..........................................................................72
26 PCI Clock Routing Guidelines......................................................................................73
27 DDR Signal Groups ...................................................................................................75
28 Supported Memory Configurations ..............................................................................78
29 DDR Command and Control Setup and Hold Values .......................................................81
30 DDR Data to DQS Read Timing Parameters ..................................................................82
31 DDR Data to DQS Write Timing Parameters..................................................................83
32 DDR-Clock-to-DQS-Write Timing Parameters................................................................84
33 Timing Relationships.................................................................................................87
34 Clock Signal Group Routing Guidelines ........................................................................89
35 Data, Command, and Control Group Routing Guidelines.................................................89
36 Clock Group Topology Transmission Line Characteristics ................................................90
37 Data Group Topology Transmission Line Characteristics .................................................93
38 Control Group Topology Transmission Line Characteristics..............................................98
39 Command Group Topology Transmission Line Characteristics........................................100
40 Control Group Topology Transmission Line Characteristics............................................105