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Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
December 2006 HDD
Document Number: 305261; Revision: 004 9
Introduction—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
1.0 Introduction
This design guide provides recommendations for hardware and system designers who
are developing with the Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network
Processors. This document should be used in conjunction with the Intel
®
IXP45X and
Intel
®
IXP46X Product Line of Network Processors Datasheet and sample schematics
provided for the Intel
®
IXDP465 Development Platform in that platform’s
documentation kit.
Design Recommendations are necessary to meet the timing and signal quality
specifications.
The guidelines recommended in this document are based on experience and simulation
work done at Intel while developing the Intel
®
IXDP465 Development Platform. These
recommendations are subject to change.
Note: This document discusses all features supported on the Intel
®
IXP465 Network
Processor. A subset of these features is supported by certain processors in the IXP45X/
IXP46X product line, such as the Intel
®
IXP460 or Intel
®
IXP455 network processors.
For details on feature support listed by processor, see the Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors Datasheet.
1.1 Content Overview
Chapter Name Description
Chapter 1.0, “Introduction” Conventions used in this manual and related documentation
Chapter 2.0, “System Architecture” System architectural block diagram and system memory map
Chapter 3.0, “General Hardware Design
Considerations”
Graphical representation of most common peripheral interfaces.
Chapter 4.0, “General PCB Guide” General PCB design practice and layer stack-up description
Chapter 5.0, “General Layout and Routing
Guide”
More specific layout and routing recommendations for board
designers
Chapter 6.0, “PCI Interface Design
Considerations”
Board-design recommendations when implementing PCI
interface
Chapter 7.0, “DDR-SDRAM”
Board-design recommendations when implementing
DDRI memory interface