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32 Intel® PXA27x Processor Family Specification Update
Errata
Status: No Fix
E39. MEMC: Memory Controller hangs when entering Self Refresh Mode.
Problem: If software manually puts SDRAM into Self Refresh Mode, then the memory controller will not
perform any more activity.
Here are the steps to recreate the issue:
1) MDREFR[K1RUN] = 1 // make sure SDCLK1 is running.
2) MDREFR[K1FREE] = 0 // turn off free running.
3) MDREFR[SLFRSH] = 1 // enter self refresh mode.
4) wait until enter Self Refresh mode.// delay approximately 2 usec.
5) Any non-SDRAM activity will not be performed by the memory controller
Implication: Will not be able to access external non-SDRAM memories after the SDRAMs are put into Self
Refresh Mode.
Workaround: The user is allowed to assert the SLFRSH bit to the memory controller placing the SDRAMs in
Self Refresh Mode, if and only if, the very next transaction the memory controller receives is the
deassertion of the SLFRSH bit. Nothing else is permitted on the memory controller after the
assertion of the SLFRSH bit, and before the deassertion of the SLFRSH bit. Essentially, this means
that the user may perform internal transfers that do not effect the memory controller, such as reads
from Instruction Cache, reads/writes to Data Cache, reads/writes to SRAM, reads/writes to internal
peripherals, but cannot perform external accesses such as VLIO or PCMCIA
Status: No Fix
E40. SDIO: SDIO Devices Not Working at 19.5 Mbps
Problem: SD/SDIO controller can only support up to 9.75 Mbps data transfer rate for SDIO card. However,
the SD/MMC card works fine at 19.5 Mbps clock rate.
The error reason is "HandleEndCommandInterrupt: response for command 52, contains a CRC
error". Other commands may respond with a CRC error also.
Many cards were tested and some fail and some pass at 19.5 Mbps, however all cards pass at 9.75
Mbps.
Test was conducted under BSP 3.00.029, V2 Beta that supports full SDIO functionality. Test was
conducted in both 1-bit and 4-bit mode and both modes fail. Test was conducted on a Mainstone
board.
The Mainstone board has an analog switch in the SDIO path. This switch, according to the spec,
can cause up to 18ns of delay. The delay causes the clock to be later at the card and then the data
gets delayed going back to the processor. According to the SD spec, the output delay maximum is
15ns @ 25MHz, or 5ns of setup time before the rising edge of the clock. This analog switch was
taken out of the circuit, however, cards were still failing.
Implication: TBD
Workaround: Slow the speed of the interface down until the card passes. This speed could be as low as 9.75
Mbps.
Status: Plan Fix