Intel® PXA27x Processor Family Power Requirements
32 Application Note
System designers can include a software-controlled threshold level detection for nVDD_FAULT to
allow an optional SDRAM keep-alive capability.
7.2 nBATT_FAULT
nBATT_FAULT indicates that the main battery is low or has been removed from the device, giving
the PXA27x processor an indication that power will shortly cease. Until that time, the processor
can operate for a limited period from a lithium/lithium manganese coin-cell backup battery, or from
a super cap that can only supply the processor for a few cycles of full-run power.
In the event of nBATT_FAULT assertion, the PXA27x processor enters an emergency form of
sleep, where the only handshaking is with external SDRAM memory (putting it into self-refresh
mode) to ensure that memory contents are preserved if possible (obviously, the refresh current can
eventually deplete the super cap or backup battery, but not as quickly as the PXA27x processor in
run mode). Supporting these features must be understood at both the board-level design and by the
PMIC.
Note: The PXA27x processor does not recognize a wakeup event while nBATT_FAULT is asserted.
If the system is powered from an AC main source (90 VAC to 240 VAC or equivalent) while
nBATT_FAULT is asserted, that fact may be used to gate off nBATT_FAULT and its normal
effects on the system. Recognition of this condition can be built into the PMIC, and a signal
indicating an AC power source is active is provided from the PMIC to the PXA27x processor
GPIO<0> or GPIO<1> signals.
8.0 Power Management Integrated Circuit
Requirements
This section provides guidelines for designing a power management integrated circuit (PMIC) for
the PXA27x processor.
8.1 General PMIC Characteristics
Table 9 shows the overall characteristics for a PXA27x processor PMIC.
