Filter
Top Products
26 Intel® PXA27x Processor Family Specification Update
Errata
@ WORKAROUND - Core hangs on voltage change at different
@ alignments and at different core clock frequencies
@ To ensure that no external fetches occur, we want to store the next
@ several instructions that occur after the voltage change inside
@ the cache. The load dependency stall near the retry label ensures
@ that any outstanding instruction cacheline loads are complete before
@ the mcr instruction is executed on the 2nd pass. This procedure
@ ensures us that the internal bus will not be busy.
@ -- Begin EnterVoltageChange__asm (void)
.section.text
.global EnterVoltageChange__asm
.align 7 @ align code to fit in one page
EnterVoltageChange__asm:
stmfd sp!, {r4}
mrs r0, CPSR @ disable interrupts
mov r4, r0
orr r0, r0, #0xC0
msr CPSR_c, r0
ldr r0, =0x41300000 @ APB register read and compare
ldr r0, [r0] @ fence for pending slow apb reads
cmp r0, #0
mov r0, #8 @ VC bit for PWRMODE
movs r1, #1 @ don’t execute mcr on 1st pass
mov r2, #0x0A000000 @ uncacheable memory to force memory read
@ CHANGE THIS ADDRESS for your environment
@ MUST be mapped into pagetable prior to
@ this function call
retry:
ldreq r3, [r2] @ only stall on the 2nd pass
cmpeq r3, #0 @ compare causes fence on memory transfers
cmp r1, #0 @ is this the 2nd pass?
mcreq p14, 0, r0, c7, c0, 0 @ write to PWRMODE on 2nd pass only
@ Read the VC bit until it is 0, indicates that the VoltageChange is done.
@ On the first pass, we never set the VC bit, so it will be clear already.
VoltageChange_loop:
mrc p14, 0, r3, c7, c0, 0
tst r3, #0x8
bne VoltageChange_loop