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28 Intel® PXA27x Processor Family Specification Update
Errata
Status: Plan Fix
E31. MEMC: SDRAM Refresh Commands are issued too often during a
VLIO access while BREQ is asserted.
Problem: During a VLIO access, if BREQ is asserted, the processor issues Refresh Commands to SDRAM
too often. This occurs after BREQ is asserted and before BGNT gets asserted. This situation lasts
for as long as VLIO CS is asserted, which can be several microseconds. During this time, the
processor is refreshing SDRAM at 100ns interval although programmed interval is around 8usec
(80x difference). Everything goes back to normal after BGNT is released.
Implication: TBD
Workaround: TBD
Status: No Fix
E32. Interrupt Controller: Unexpected exception vector when ICCR[DIM]=0
and ICMR=0.
Problem: When ICCR.DIM = 0 and ICMR = 0 and a direct key press is performed, the Interrupt Control IRQ
Pending (ICIP) register, does not indicate a pending interrupt after coming up from idle, but the
core attempts to vector to an exception vector address (0x000 to 0x01C).
If ICMR=0x0 and ICCR[DIM]=0b0 and a direct key press is performed, then the correct behavior
should be:
After the key is pressed, the processor wakes from IDLE, ICPR gets updated, the ICIP (or ICFP)
does not get updated, and the processor should not vector to any vector address (0x00 to 0x1C).
The incorrect behavior is:
After the key is pressed, the processor wakes from IDLE, ICPR gets updated, the ICIP (or ICFP)
does not get updated, but the processor tries to vector to 0x18 (for IRQ handler) or 0x1C (for FIQ
handler), based on the contents of ICLR.
Keypad and DIM Bit and ICMR test failure:
ICCR = 0x00000000, ICMR = 0x04000000.
KPC = 0x000001C3; KPC[DIE] = 1; KPC[DE] = 1;
KPKDI[DIRECT KEY DEBOUNCE INTERVAL] = 20 (msec).
Implication: TBD
Workaround: Code below disables interrupts to the core before going to Idle and re-enables core interrupts after
returning from Idle.
IDLE:
.global IDLE
mrs r0, cpsr @ read current processor status register
orr r0, r0, #0xC0 @ disable core interrupts
msr cpsr_c, r0 @ update the current processor status register
mov r0, #1
mcr p14, 0, r0, c7, c0, 0 @ Set IDLE
mrc p14, 0, r0, c7, c0, 0 @ CPWAIT ROUTINE