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Intel® PXA27x Processor Family Specification Update 37
Errata
5. A GPIO<1:0> edge is asserted
then there is no guarantee that the processor will wake from sleep mode.
Implication: There is no guarantee that the processor will wake up from sleep mode, if the PWER[1:0] is
cleared, and a nVDD_FAULT or nBATT_FAULT is asserted during the sleep mode, and then a
GPIO<1:0> edge is asserted.
Workaround: Any of the following workarounds can be used:
1. Keep PWER bit corresponding to the wakeup enabled before entering sleep.
2. Assert GPIO wakeup signal(s) while the fault is asserted.
3. Keep the 13 MHz oscillator running during sleep mode.
Status: No Fix
E50. POWER MANAGER: The processor does not exit from sleep/deep-
sleep mode.
Problem: The processor is exhibiting a problem when waking up from sleep and deep-sleep mode. Specifi-
cally, the issue is a race condition between clocks in the processor’s sleep/deep-sleep wakeup
circuitry. When the processor begins to wake from sleep/deep-sleep mode, a reset to the clock unit
de-asserts while the internal power and ground supplies to the wakeup circuitry are not yet stable.
The effect is that parts of the clock unit will be in an unknown state after the reset has been de-
asserted. In most cases, the race condition will end successfully without de-asserting the reset too
early and the issue will not be seen. However, in a small number of parts, the reset de-asserts too
early, thus causing the issue.
Implication: Early release of the reset prior to a good, stable power and ground supply can lead to unpredictable
values during wakeup and can result in the processor stopping execution. The Erratum is also
manufacturing process dependent and intermittent, so only a small percentage of devices are
ultimately affected.
Workaround: Intel has found that keeping VCC_Core powered during sleep mode seems to prevent the
predictable behavior because it helps keep the correct state of the wakeup circuitry, even when the
reset to the wakeup circuitry is de-asserted early. Additional testing has also shown that entering
sleep mode at 91 MHz with VCC_Core at 0.95V (+/- 5%), but then grounding VCC_Core during
sleep helps to alleviate the issue in a large number of cases, but not all. Finally, the processor’s
watchdog timer can be implemented to reset the processor, if the failure occurs. This gives
customers the ability to gracefully handle a system failure due to this erratum. Use of the potential
workarounds can help greatly reduce or possibly eliminate the occurrence of the erratum. Details of
these workarounds can be found in the following Application Note: Sleep/Deep-Sleep Exit
Procedure for the Intel® PXA27x Processor Family.
Status: Plan Fix
E51. SDIO: CMD53 multiple-block data transfer with block count set to 0
not supported.
Problem: A block count of 0 for CMD53 is not supported.
Implication: The block count field in CMD53 is 9 bits (511 maximum blocks). To send more than 511 blocks,
set the block count in CMD53 to 0 in the command argument. The PXA27x SDIO controller does
not support this functionality.
Workaround: If more than 511 blocks are to be transferred, software should send multiple CMD53 multi-block
transfers with a block count that is <= 511.
Status: No Fix