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Intel® PXA27x Processor Family Specification Update 29
Errata
mov r1, r1 @ CPWAIT ROUTINE
sub pc, pc, #4 @ CPWAIT ROUTINE
mrs r0, cpsr @ read current processor status register
bic r0, r0, #0xC0 @ enable core interrupts
msr cpsr_c, r0 @ update the current processor status register
mov pc, r14 @ RETURN
Status: No Fix
E33. SSP: TXD line does not tristate when SSP is Slave to Frame
Problem: When the SSP is a Slave to Frame (SFRMDIR=1) and Master of Clock (SCLKDIR=0) using the TI
SSP Format, the SSP will not tri-state the TXD line at the end of the last frame when the TTE=1
and TTELP=1 and the SCR>3.
When TI protocol is used, the SSP unit is Slave to Frame and Master/Slave to clock, TTE=1,
TTELP = 1, Data Size = 4.
When a data value of 0xA is transmitted, the last data bit is zero, and when a pullup is applied to
the TXD pin, the line should go high, but it always remains low.
Similarly, when a data value of 0x5 is transmitted, the last data bit is one, and when a pull-down is
applied to the TXD pin, the line should go low, but it always remains high.
When TTE=1, TTELP = 0 is used, the TXD line will tristate at the beginning and end of transfer.
Also, the TXD line works fine when the SSP is Master to Frame.
Implication: TBD
Workaround: None.
Status: No Fix
E34. PowerManager: Simultaneous BATT and VDD faults results in going
to DeepSleep mode twice.
Problem: When in any mode, asserting simultaneous BATT_FAULT and VDD_FAULT signals, and while
BIDAE is not equal to VIDAE, requires the user to go to DeepSleep twice, once automatically due
to one of the xIDAE bits being clear, and once via software due to one of the xIDAE bits being set.
Another observation is that a very short (approx. 332usec) nRESET_OUT assertion occurs
followed by a bootup (with no change to RCSR).
Implication: TBD
Workaround: PMCR[BIDAE] and PMCR[VIDAE] must be identical.
Status: No Fix
E35. CORE: Non-branch instruction in vector table may execute twice after
a thumb mode exception
Problem: If an exception occurs in thumb mode and a non-branch instruction is executed at the corre-
sponding exception vector, that instruction may execute twice. Typically, instructions located at
exception vectors must be branch instructions which go to the appropriate handler, but the ARM
architecture allows the FIQ handler to be placed directly at the FIQ vector (0x0000001c/
0xffff001c) without requiring a branch.