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Intel® PXA27x Processor Family Specification Update 15
Errata
trouble on the trace interface, which results in the core reporting the event as if it came with the
next instruction executed after the aborting lock instruction, the data abort vector.
Implication: TBD
Workaround: None.
Status: No Fix
E6. CORE: CP15 ID register accesses with opcode2 > 0b001 return unpre-
dictable values.
Problem: The XScale core does not implement CP15 ID codes registers other than the Main ID register
(opcode2 = 0b000) and the Cache Type register (opcode2 = 0b001). If any of the unimplemented
registers are accessed by software (for example, mrc p15, 0, r3, c15, c15, 2), the value of the Main
ID register should be returned. Instead, an unpredictable value is returned.
Implication: TBD
Workaround: None.
Status: No Fix
E7. CORE: Disabling and re-enabling the MMU can hang the core or
cause it to execute the wrong code.
Problem: If the MMU is disabled via the CP15 control register after being enabled, certain timing cases can
cause the processor to hang. In addition, re-enabling the MMU after disabling it can cause the
processor to fetch and execute code from the wrong physical address. To avoid these issues, the
code sequence below must be employed whenever disabling the MMU or re-enabling it afterwards.
Implication: TBD
Workaround: The following code sequence must be used to disable and/or re-enable the MMU safely. The
alignment of the mcr instruction that disables or re-enables the MMU must be controlled carefully,
so that it lies in the first word of an instruction cache line:
;//@ The following code sequence takes r0 as a parameter. The value of r0 will be
;//@ written to the CP15 control register to either enable or disable the MMU.
mcr p15, 0, r0, c10, c4, 1 ;// @ unlock I-TLB
mcr p15, 0, r0, c8, c5, 0 ;//@ invalidate I-TLB
mrc p15, 0, r0, c2, c0, 0 ;//@ CPWAIT
mov r0, r0
sub pc, pc, #4
b AfterAlign ;//@ branch to aligned code
ALIGN 32 ;//@ align to 32 bytes
AfterAlign
mcr p15, 0, r0, c1, c0, 0 ;//@ enable/disable MMU, caches
mrc p15, 0, r0, c2, c0, 0 ;//@ CPWAIT
mov r0, r0
sub pc, pc, #4
Status: No Fix