Intel PXA27X Computer Hardware User Manual


 
24 Intel® PXA27x Processor Family Specification Update
Errata
Step 4: a. Now Overlay 2 in YUV 420 mode is enabled and running.
Step 5: a. If Overlay 2 needs to be disabled, Disable the Overlay 2 by writing to O2CR1 and
Frame Branch Registers (FBRx).
b. If the Overlay 2 needs to be enabled again, Go to Step 3.
Step 6: a. If LCD needs to disabled, disable the Overlay 2 as mentioned in Step 4, then
Disable LCD, and go to Step 1.
Pseudo Code to Enable RGB Mode:
Write ovl2c2
Write ovl2c1 (O2EN = 1)
Write fdadr2
Pseudo Code to Disable RGB Mode:
Write ovl2c1 (O2EN = 0)
Clear LCSR1 BS2 bit (LCSR1 = 0x200
Write fbr2 (BRA=BRANCH_AFTER_CURRENT_FRAME, BINT=SET_SR_BS_BIT)
Wait for branch to complete (LCSR1 == 0x200)
Pseudo Code to Enable 4:2:0 mode:
Write ovl2c2
Write ovl2c1 (O2EN = 1)
Clear LCSR1 IU2 bit (LCSR1 = 0x02000000);
Wait for under-run LCSR1 = 0x02000000
Write fdadr2
Write fdadr3
Write fdadr4
Pseudo Code to Disable 4:2:0 mode:
Write ovl2c1 (O2EN = 0)
Clear LCSR1 BS2 bit (LCSR = 0xe00)
Write fbr2 (BRA=BRANCH_AFTER_CURRENT_FRAME BINT=SET_SR_BS_BIT)
Write fbr3 (BRA=BRANCH_AFTER_CURRENT_FRAME BINT=SET_SR_BS_BIT)
Write fbr4 (BRA=BRANCH_AFTER_CURRENT_FRAME BINT=SET_SR_BS_BIT)
Wait for branch to complete (LCSR1=0xe00)
Status: Plan Fix
E26. USBOTG: Unable to measure duration of Single-Ended Zero (SE0) for
Session Request Protocol (SRP)
Problem: According to On-the-Go Supplement to the USB 2.0 Specification, we must be able to detect that a
Single-Ended Zero (SE0) condition is driven on the USB bus for at least 2 ms before we can
initiate a Session Request Protocol (SRP). See paragraph below.