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Intel® PXA27x Processor Family Specification Update 23
Errata
E23. ICP: Receiver Aborts randomly occur prematurely and without End of
frame/Error in FIFO interrupt
Problem: Randomly, Receiver Abort (ICSR0[RAB]=1) occurs prematurely and without the EOF status/
interrupt bit set (ICSR1[EOF]=1). When this event occurs, there is always 2 bytes left in the RX
FIFO.
A Receiver Abort should always cause an EOF, but in the failing cases, only the Receiver Abort is
set.
Adding ~15us delay to the receive data available interrupt (IIR[IID]=0b10) service routine causes
this failing case to pass, but limits the transfer size to the size of the FIFO since the added delay
will cause an overrun condition.
Implication: TBD
Workaround: Software must do retries after RAB has occurred. Once a RAB event occurs, continue to read data
out of the FIFO until the EOF flag sets, then throw away all the data of that frame, and then make a
request to the host to resend/retry the last frame of data again.
Status: No Fix
E24. SSP: OSTimer counter increments incorrectly for SSP Frames in
Network mode
Problem: When SSP unit is in network mode, when PSP protocol is used, and the SSP is master to Frame
(irrespective of sspsclk direction) and FSRT bit is set to 1, OStimer frame counter increments more
than the frame is asserted by SSP. For example, 11 frames are asserted as seen on a logic analyzer,
but OStimer is showing that the frame signal is asserted for 12 times. OS timer works fine when
FSRT is cleared and when in non-network mode.
Implication: TBD
Workaround: Subtract one from the value that is read from the OSTimer frame counter.
Status: No Fix
E25. LCD: Enabling Overlay 2 for YUV420 hangs LCD controller.
Problem: Enabling Overlay 2 in YUV 420 mode causes the LCD controller to stop operating (DMA activity
stops and the screen fades away). The test is unable to gracefully shutdown the LCD controller
after this failure.
Enabling Overlay 2 in RGB mode has no problems.
Implication: TBD
Workaround: To Enable/Disable Overlay 2 in 4:2:0 mode:
Step 1: a. Enable the LCD with Overlay2 disabled.
Step 2: a. Enable Overlay 2 in RGB mode with minimum size possible so that only one frame
worth of data fit in Channel 2 FIFO. Size of Channel 2 FIFO is 128 bytes. Program
the Descriptors and write to O2CR1.
b. Run at least 1 frame with Overlay 2.
c. Disable the Overlay 2 by writing to O2CR1 and Frame Branch Registers (FBRx).
d. Wait for 3 base EOF interrupts.
Step 3: a. Enable Overlay 2 in YUV 420 mode. Write to O2CR1.
b. Unmask/Clear the input underrun for Channel 2. Wait for input underrun from
Channel 2. Write DMA descriptors for Channels 2, 3, and 4.