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Intel® PXA27x Processor Family Specification Update 25
Errata
Sec. 5.3.2..."A second initial condition for starting a new session is that the B-device must detect
that both the D+ and D- data lines must have been low (SE0) for at least 2 ms (TB_SE0_SRP min.).
This ensures that the A-device has detected a disconnect condition from the device.”...
Software has the ability, through reset interrupt, to see when the SE0 state was entered, but it has no
way to determine how long it has been in this state, to determine if the 2 ms requirement has been
met.
Implication: Dual role devices (A and B devices) are required to be able to initiate and respond to an SRP,
therefore, there is the potential that the USB OTG will not pass a USB OTG compliance test.
Workaround: The USB OTG specification says, in section 5.3.2:
"A second initial condition for starting a new session is that the B-device must detect that both the
D+ and D- data lines must have been low (SE0) for at least TB_SE0_SRP min. This ensures that
the A-device has detected a disconnect condition from the device." Currently, TB_SE0_SRP is
specified at 2 msec minimum.
The workaround is to require VBUS to be low for at least 2 msec, and assume that the data lines are
low, if VBUS is low. This assumption would work for devices that make the same assumption, but
nothing in the specification requires this.
Status: Plan Fix
E27. MEMC: Write/Read to/from SDRAM can collide with alternate bus
master mode when MDREFR:ALTREFB is set.
Problem: When ALTREFB is programmed to 1 and an alternate bus master requests the bus, an SDRAM
access in progress may not be allowed to finish before the bus is released. This issue is found in
both fly-by mode and non-fly-by mode.
Currently, there is a provision in the specification that ALTREFA and ALTREFB cannot both be set
at the same time. Given the workaround below, this will only allow the refreshes to occur both
before and after an alternate bus master, or only before an alternate bus master.
Implication: This will potentially cause more refreshes than is necessary according to the SDRAM specifi-
cation.
Workaround: Never set MDREFR[ALTREFB]. This will cause a refresh cycle to always occur before allowing
an alternate bus master to be granted the bus.
Status: No Fix
E28. Power Manger: Core hangs during voltage change when there are
outstanding transactions on the bus
Problem: If coprocessor 14 register 7 is written for a voltage change sequence (PWRMODE[VC] = 0b1) and
there are outstanding core transactions on the internal bus, the core hangs.
Implication: Unpredictable results can occur if the core hangs.
Workaround: The workaround is to make sure all core transactions are complete and no new core transactions
will attempt to get on the internal bus, then initiate a voltage change by setting PWRMODE[VC],
then waiting until the PWRMODE[VC] bit is cleared. The VC bit will be cleared within 50ns of the
voltage change initiation. If software requires the entire voltage change sequence to complete, i.e.
no more communication with the external power manager IC, the software must wait until the
PVCR[VCSA] bit is clear.
The following workaround has been tested and will handle all cases.