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Intel® PXA27x Processor Family Specification Update 33
Errata
E41. AC97: Command Done bit is never set when data is written in slot12
Problem: The “Codec Done Bit” does not get set upon completion of a write to register 0x54 in Modem IO
Space. Moreover, no AC97 controller interrupt will occur to the CPU, telling the software that a
register write to 0x54 is complete.
Implication: TBD
Workaround: Software must poll the CAIP bit to determine if a write was accomplished.
Status: No Fix
E42. SD/MMC: SD/MMC controller CRC errors with some SD/MMC cards
Problem: In MMC/SD/SDIO cards, not in SPI mode, CMD2, CMD9, and CMD10 use an R2 type Response.
An R2 Response is a 136 bit Response, where:
— [135:128] is 0x3F
— [127:1] is the register being read, where bits [7:1] is the CRC for bits [127:8] of the
register
— [0] is the END bit, which is always 1.
The controller ignores bits [135:128] for CRC checking.
The controller should use bits [127:1] for CRC checking. The problem is that the controller is using
bits [126:1] for CRC checking. If bit 127 is a 0, then there is no problem, because the CRC checker
is always initialized to 0. However, if bit 127 is a 1, then a response CRC error will occur.
Implication: TBD
Workaround: If a Response CRC error occurs for CMD2, CMD9, or CMD10, and bit 127 is a 1, ignore the error.
Status: Plan Fix
E43. USBH: There is no Individual Power Sense Polarity bit for each Host
Port. The Power Sense Polarity bit controls the polarity for all three
Host Ports.
Problem: Overcurrent indicator signals for Host Port 1 and 2 are controlled externally by USBHPWR[2:1].
Overcurrent indicator signal for Host Port 3 is not pinned out to an external pin. This signal is
internally tied to ground.
The Power Sense Polarity bit (UHCHR[PSPL]) controls the polarity of the Overcurrent indicator
signals for all three Host Ports.
If a usage model requires that the polarity of the Host Port 1 or 2 be active low, then this will cause
a false overcurrent indication to occur on Host Port 3.
Also, software cannot ignore overcurrent on just Host Port 3. Ignoring overcurrent can only be
done across all three ports by setting UHCRHDA[NOCP].
The intended silicon fix is to disconnect the Host Port 3 Overcurrent indicator signal from internal
ground and connect it to the Power Sense Polarity (PSPL) bit. This guarantees that Host Port 3 will
never see an overcurrent condition.
Note that when switching PSPL, a small glitch might be seen on the Overcurrent indicator for Host
Port 3. This should not be an issue since the usage model for PSPL is that it is designed to be set
statically at initialization time.