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Intel® PXA27x Processor Family Specification Update 21
Errata
the loop to read out the data, the test never fails. So the issue looks to be related to the amount of
time between reading data out of the FIFO.
Pseudo Code for the Character Timeout Interrupt Handler routine test:
1. Read LSR and check for errors
2. Read Data from FIFO
3. Software Delay (Delay increases after each test)
4. Read LSR, check for errors, and LOOP back to (2) if DR is SET.
5. DONE
if step (3) is placed in front of step (1) the issue never occurs.
Implication: The software servicing the UART can be trapped in an infinite loop.
Workaround: Steps 2 and 6 have been added to the Interrupt Handler routine. Disabling the Receiver Time-Out
interrupt via IER[RTOIE] (step 2) prevents the Receiver Time-Out interrupt from becoming
continuously set.
1. Read the Line Status Register (LSR) and check for errors
2. Disable the Receiver Time-Out interrupt via IER[RTOIE]
3. Read Data from the UART FIFO
4. Software Delay (Increments after each test)
5. Read LSR, check for errors, and LOOP back to (2) if DR is SET.
6. No more data in FIFO: Re-enable RTO interrupt via IER[4]
7. DONE
Therefore, users must disable the Receiver Time-Out interrupt, then read data from the FIFO, then
re-enable the Receiver Time-Out interrupt, before exiting the handler routine.
Status: No Fix
E21. LCD: LCD not enabling in dual panel mode.
Problem: After the LCD unit is dynamically changed from single panel mode to dual panel mode, the LCD
unit will not output any data on the LCD pins.
Implication: TBD
Workaround: Do the following sequence to change from single panel mode to dual panel mode:
Configure the LCD to Single panel mode
Enable the LCD
Disable the LCD
Reconfigure the LCD to Dual Panel mode without programming the DMA registers.
Enable the LCD
Do a quick disable (not normal disable).
Program the LCD DMA registers
Enable the LCD for operation in Dual Panel mode.
Status: No Fix