Filter
Top Products
Intel® PXA27x Processor Family Specification Update 35
Errata
• When the USB is in transceiverless mode (UP3OCR[CFG] = 0x2), then USB_P3_6 (VPO)
and USB_P3_4 (VMO) are not ignored by USB Host Port 3 when USB_P3_2 (OE_n) is
deasserted.
• However, this will allow the following conditions:
— USB Host Port 3 in Transceiverless Mode can be connected to a fast speed (12Mbps)
device or slow speed (1.5Mbps) device.
— The USB device can use the common method of indicating a fast speed device connection
by pulling the VPO line high, or a slow speed device connection by pulling the VMO line
high, or disconnect by pulling both VPO and VMO low.
Implication: TBD
Workaround: Use a 2-input OR gate, with one input connected to OE_n from the device, the other input
connected to VPO from the device, and the output connected to USB_P3_6 (VPO) of the
processor.
Status: Plan Fix
E46. SD/MMC: SPI mode commands fail even on cards that are compatible
with SPI spec 1.0
Problem: When the SD/MMC controller is put into SPI mode, all read commands where data is transmitted
in the DATA token, will fail, even if the card is SPI spec 1.0 compliant.
For example:
• C0 step silicon:
— CMD9/CMD10 failed on cards compatible with SPI spec 1.0
— CMD9/CMD10 failed on cards compatible with SPI spec 1.0.1
Another example:
• CMD52 can do 1 byte reads. The read data is returned in the Response Token and there is no
data transfer on DAT line. Therefore, this command will pass.
• CMD53 can read multiple bytes and blocks. The read data is returned on the DAT line.
Therefore, this command will fail.
Implication: When the SD/MMC controller is put into SPI mode, all read commands where data is transmitted
in the DATA token, will fail.
Workaround: Do not use SD/MMC in SPI mode or use Read Commands that return data in the Response Token.
Status: Plan Fix
E47. CLOCKS AND POWER: PWM Clock Enables do not work as specified
Problem: According to the specification, CKEN[0] controls the PWM0 and PWM2 Clock Enable, and
CKEN[1] controls the PWM1 and PWM3 Clock Enable. However, CKEN[0] and CKEN[1] both
have to be disabled in order to disable any of the PWMx clocks.