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30 Intel® PXA27x Processor Family Specification Update
Errata
Implication: The first instruction in thumb mode of a FIQ handler may be executed twice if it is not a branch
instruction.
Workaround: If a no-op is placed at the beginning of the FIQ handler, the no-op will execute twice and no
incorrect behavior will result. If a branch instruction is placed at the beginning of the handler, it
will not be executed twice.
Status: No Fix
E36. UART: UART does not correctly indicate a Framing Error Interrupt in
DMA mode.
Problem: When DMA is enabled and a "Framing Error" occurs, the UART generates an interrupt, but the IIR
register does not show any pending interrupts (IIR[nIP]=0b1).
Reading the registers does not clear the interrupt. The UART will continuously interrupt the
CORE.
If the RX FIFO is emptied until there is only 4 bytes of data left in the FIFO, the UART will finally
generate a RLS interrupt showing a "framing" error.
The UART handles errors differently in DMA mode. When an error occurs the error gets tagged in
the rx fifo with the erroneous byte. In interrupt mode, the error is flagged (processor interrupted)
when the erroneous byte is read out of the bottom of the fifo. In DMA mode, the error is flagged as
soon as it is detected. In DMA mode, the UART correctly interrupts the processor when the error is
first detected but it does not update the IIR register until the error is read out of the FIFO. Thus, the
processor is interrupted with no interrupt pending. The correct operation is to both interrupt the
processor and update the IIR register when the error is detected.
Implication: The UART generates an interrupt, but the IIR register does not show any pending interrupts.
Workaround: If an interrupt is generated, but the IIR register does not show any pending interrupts, then read
data out of the RX FIFO until either it is empty or a valid interrupt is generated. The error interrupt
to the core will not clear until the erroneous byte is read out of the RX FIFO.
Status: No Fix
E37. CLOCKS: System Hangs when enabling RUN/TURBO switching at
520MHz
Problem: The system will hang when performing switching from Run Mode frequency to Turbo Mode
frequency.
The test flow is as follows:
—Bootup
— Perform a Frequency / Voltage change to L=16, N=2.5, A=1, B=1, K0DB4=1,
K1DB2=1,K2DB2=1. This gives core = 208MHz (run mode), Sys Bus = 208MHz, and
MEMC = 208MHz. Note the Turbo bit (T) is not set yet.
— Display a code of “0xFFAA0000”
— Go to Turbo mode by setting the Turbo bit.
— Display a code of “0xFFBB0000”