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Intel® PXA27x Processor Family Specification Update 27
Errata
subs r1, r1, #1 @ update conditional execution counter
beq retry
msr CPSR_c, r4 @ restore interrupts to original state
ldmfd sp!, {r4}
mov pc, lr
.data
@ -- End EnterVoltageChange__asm
Status: No Fix
E29. MMC: MMC unit in SPI mode always waits a minimum of 1 Ncx cycles,
even though the MMC spec dictates that SPI mode CMD9 can have a
minimum of 0 Ncx cycles.
Problem: The MMC unit is not compliant with the MMC Spec 3.2 in SPI Mode.
Version 2.11 of the MMC Spec, in SPI mode, requires 1 or more Ncr cycles between the end of the
response and the beginning of the data block for CMD9 (SEND_CSD command).
Version 3.1 and 3.2 of the MMC Spec, in SPI mode, requires 0 or more Ncx cycles between the end
of the response and the beginning of the data block for CMD9 (SEND_CSD command).
The MMC unit always waits a minimum of 1 Ncx cycle between the response and the data block,
therefore, MMC unit is not compliant with the version 3.2 of the Spec.
Implication: TBD
Workaround: TBD
Status: Plan Fix
E30. SD: SD Controller in SPI mode not receiving data response for CMD9
and CMD10 from some SD Cards
Problem: The SD unit is not compliant with SD Spec 1.01 in SPI Mode.
Version 1.0 of the SD Spec, in SPI mode, requires 1 or more Ncr cycles between the end of the
response and the beginning of the data block for CMD9 (SEND_CSD command).
Version 1.01 of the SD Spec, in SPI mode, requires 0 or more Ncx cycles between the end of the
response and the beginning of the data block for CMD9 (SEND_CSD command).
The SD unit always waits a minimum of 1 Ncx cycle between the response and the data block,
therefore, the SD unit is not compliant with the 1.01 Spec.
Implication: TBD
Workaround: TBD