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Problem Solving
Table 6-3. POST Tests (continued)
Code Beeps POST Routine Description
40 2-1-1-1 Set Initial CPU speed
42 1-1-1-3 Initialize interrupt vectors
44 2-1-2-1 Initialize BIOS interrupts
46 2-1-2-3 Check ROM copyright notice
47 2-1-2-4 Initialize manager for PCI Option ROMs
48 2-1-3-1 Check video configuration against CMOS
49 2-1-3-2 Initialize PCI bus and devices
4A 2-1-3-3 Initialize all video adapters in system
4C 2-1-4-1 Shadow video BIOS ROM
4E 2-1-4-3 Display copyright notice
50 2-2-1-1 Display CPU type and speed
52 2-2-1-3 Test keyboard
54 2-2-2-1 Set key click if enabled
56 2-2-2-3 Enable keyboard
58 2-2-3-1 Test for unexpected interrupts
5A 2-2-3-3 Display prompt “Press F2 to enter SETUP”
5C 2-2-4-1 Test RAM between 512 and 640K
60 2-3-1-1 Test extended memory
62 2-3-1-3 Test extended memory address lines
64 2-3-2-1 Jump to User Patch1
66 2-3-2-3 Configure advanced cache registers
68 2-3-3-1 Enable external and CPU caches
6A 2-3-3-3 Display external cache size
6C 2-3-4-1 Display shadow message
6E 2-3-4-3 Display non-disposable segments
70 2-4-1-1 Display error messages
72 2-4-1-3 Check for configuration errors
74 2-4-2-1 Test real-time clock
76 2-4-2-3 Check for keyboard errors
7C 2-4-4-1 Set up hardware interrupt vectors
7E 2-4-4-3 Test coprocessor if present
80 3-1-1-1 Disable onboard I/O ports
82 3-1-1-3 Detect and install external RS232 ports
84 3-1-2-1 Detect and install external parallel ports
86 3-1-2-3 Reinitialize onboard I/O ports