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4513/4514 Group User’s Manual
APPLICATION
2-9
2.1 I/O pins
2.1.4 Notes on use
(1) Note when an I/O port except port P5 is used as an input port
Set the output latch to “1” and input the port value before input. If the output latch is set to “0,” “L”
level can be input.
(2) Noise and latch-up prevention
Connect an approximate 0.1
µ
F bypass capacitor directly to the VSS line and the VDD line with the
thickest possible wire at the shortest distance, and equalize its wiring in width and length.
The CNVSS pin is also used as the VPP pin (programming voltage = 12.5 V) at the built-in PROM
version.
Connect the CNVSS/VPP pin to VSS through an approximate 5 kΩ resistor which is connected to the
CNVSS/VPP pin at the shortest distance.
(3) Note on multifunction
The input of D6, D7, P20–P22, CMP0-, CMP0+, CMP1-, CMP1+ and the input/output of P30, P31,
P40–P43 can be used even when CNTR0, CNTR1, SCK, SOUT, SIN, AIN0–AIN3, INT0, INT1, and AIN4–
AIN7 are selected.
(4) Connection of unused pins
Table 2.1.6 shows the connections of unused pins.
(5) SD, RD instructions
When the SD and RD instructions are used, do not set “10002” or more to register Y.
(6) Analog input pins
When both analog input AIN4–AIN7 and I/O port P4 function are used, note the following;
• Notes when selecting analog input pins
Even when register Q2 is used to set the pins for analog input, P40/AIN4–P43/AIN7 continue to
function as P40–P43 I/O. Accordingly, when any of them are used as I/O port P4 and others are
used as analog input pins, make sure to set the outputs of pins that are set for analog input to
“1.” Also, for the port input, the port input function of the pin functions as analog input is undefined.
(7) Notes on port P3
In the 4513 Group, when the IAP3 instruction is executed, the contents of high-order 2 bits of register
A are undefined.