Filter
Top Products
APPLICATION
2.3 Timers
2-34
4513/4514 Group User’s Manual
0
b3 b0
➀ Disable Interrupts
Timer 2 interrupt is temporarily disabled.
Interrupt enable flag INTE
Interrupt control register V1
“0”
✕✕✕
All interrupts disabled (DI instruction)
Timer 2 interrupt occurrence disabled
(TV1A instruction)
b3 b0
00
➁ Stop Timer Operation
Timer 1 operation is temporarily stopped.
Timer 2 count source is selected.
Timer control register W2
✕
Timer 2 stop (TW2A instruction)
CNTR0 input selected for count source
1
➂ Set Timer Value
Timer 2 count time is set.
Timer 2 reload register R2
“63
16
”
Timer count value 99 set (T2AB instruction)
g0 h
➃ Clear Interrupt Request
Timer 2 interrupt activated condition is cleared.
Timer 2 interrupt request flag T2F
“0”
Timer 2 interrupt activated condition cleared
(SNZT2 instruction)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag T2F, insert the NOP instruction after the SNZT2 instruction.
➄ Start Timer 2 Operation
Timer 2 temporarily stopped is restarted.
Timer 2 operation start (TW2A instruction)
b3 b0
10
Timer control register W2
✕
1
b3 b0
1
➅ Enable Interrupts
The timer 2 interrupt which is temporarily disabled is enabled.
Interrupt control register V1
Interrupt enable flag INTE
“1”
Timer 2 interrupt occurrence enabled
(TV1A instruction)
All interrupts enabled (EI instruction)
✕✕✕
“✕”: it can be “0” or “1.”
Fig. 2.3.5 CNTR1 input setting example
However, specify the pulse width input to CNTR0 pin/CNTR1 pin. Refer to section “2.3.4 Notes on use” for
the timer external input period condition.