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4513/4514 Group User’s Manual
HARDWARE
1-25
FUNCTION BLOCK OPERATIONS
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt en-
able bits (V10–V13 and V20–V23), and interrupt request flag are
“1.” The interrupt actually occurs 2 to 3 machine cycles after the
cycle in which all three conditions are satisfied. The interrupt oc-
curs after 3 machine cycles only when the three interrupt condi-
tions are satisfied on execution of other than one-cycle instructions
(Refer to Figure 16).
Fig. 16 Interrupt sequence
T
1
T
2
T
3
T
1
T
2
T
3
T
1
T
2
T
3
System clock
T
1
T
2
T
3
EXF0, EXF1
T1F, T2F, T3F,
T4F, ADF,SIOF
INT0, INT1
T
1
T
2
T
3
2 to 3 machine cycles
(Notes 2, 3)
The program starts from
the interrupt address.
Flag cleared
Interrupt enabled state
When an interrupt request flag is set after its interrupt is enabled (Note 1)
1 machine cycle
EI instruction
execution cycle
Interrupt enable
flag (INTE)
Retaining level of system
clock for 4 periods or more
is necessary.
Interrupt disabled state
External
interrupt
Timer 1,
Timer 2,
Timer 3,
Timer 4,
A-D, and
Serial I/O
interrupts
Interrupt activated
condition is satisfied.
2: The address is stacked to the last cycle.
3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
Notes 1: The 4513/4514 Group operates in the middle-speed mode after system is released from reset.
f (X
IN
) (middle-speed mode)
f (X
IN
) (high-speed mode)