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4513/4514 Group User’s Manual
HARDWARE
1-43
FUNCTION BLOCK OPERATIONS
Table 16 Change of successive comparison register AD during A-D conversion
Comparison voltage (Vref) value
Change of successive comparison register ADAt starting conversion
±
±
±
±
±
(7) Operation description
A-D conversion is started with the A-D conversion start instruction
(ADST). The internal operation during A-D conversion is as follows:
➀ When A-D conversion starts, the register AD is cleared to
“00016.”
➁ Next, the topmost bit of the register AD is set to “1,” and the
comparison voltage Vref is compared with the analog input volt-
age VIN.
➂ When the comparison result is Vref < VIN, the topmost bit of the
register AD remains set to “1.” When the comparison result is
Vref > VIN, it is cleared to “0.”
The 4513/4514 Group repeats this operation to the lowermost bit of
the register AD to convert an analog value to a digital value. A-D
conversion stops after 62 machine cycles (46.5
µ
s when f(XIN) =
4.0 MHz in high-speed mode) from the start, and the conversion re-
sult is stored in the register AD. An A-D interrupt activated condition
is satisfied and the ADF flag is set to “1” as soon as A-D conversion
completes (Figure 27).
✼1: 1st comparison result
✼3: 3rd comparison result
✼9: 9th comparison result
✼2: 2nd comparison result
✼8: 8th comparison result
✼A: 10th comparison result
1st comparison
2nd comparison
3rd comparison
After 10th comparison
completes
1
✼1
✼1
✼1
-----
-----
-----
-----
0
1
✼2
✼2
0
0
1
✼3
0
0
0
✼8
0
0
0
✼9
0
0
0
✼A
A-D conversion result
VDD
2
VDD
2
VDD
2
VDD
2
VDD
4
VDD
4
VDD
8
VDD
1024
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