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TCK
GND
TEST/VPP
VCC TOOL
VCC TARGET
J2 (see Note A)
V
CC
R1
47 k
(see Note B)
W
C2
10 µF
C3
0.1 µF
V /AV /DV
CCCC CC
RST/NMI/SBWTDIO
MSP430Fxxx
C1
2.2 nF
(see Note B)
TEST/SBWTCK
V /AV /DV
SS SS SS
J1 (see Note A)
JTAG
TDO/TDI
1
3
5
7
9
11
13
2
4
6
8
10
12
14
R2
330
(see Note C)
W
Signal Connections for In-System Programming and Debugging
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A Make either connection J1 in case a local target power supply is used or connection J2 to power target from the
debug/programming adapter.
B The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access and that any capacitance attached to this signal may affect the ability to establish a connection with the
device. The upper limit for C1 is 2.2 nF when using current TI FET interface modules (USB FET).
C R2 protects the JTAG debug interface TCK signal from the JTAG security fuse blow voltage that is supplied by the
TEST/VPP pin during the fuse blow process. If fuse blow functionality is not needed, R2 is not required (populate
0 ?), and do not connect TEST/VPP to TEST/SBWTCK.
Figure 2-2. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
26
Design Considerations for In-Circuit Programming SLAU278F–May 2009–Revised December 2010
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