Major Chips Description 2-3
• UMA (unified memory architecture)
• Dedicated UMA arbiter pins
• Supports several protocols from major graphics vendors
• SFB size : 512KB/1MB/2MB/3MB/4MB
• CPU could access frame buffer memory through system memory controller
• Alias address for frame buffer memory
• Fully synchronous 25/30/33 MHz 5V PCI interface
• PCI bus arbiter: five PCI masters and M1523 supported
• Dwords for CPU-to-PCI Memory write posted buffers
• Convert back-to-back CPU to PCI memory write to PCI burst cycle
• DWORDS for PCI-to-DRAM write-posted/read-prefetching buffers
• PCI-to-DRAM up to 133 MB/sec bandwidth (even when L1/L2 write-back)
• L1/L2 pipelined snoop ahead for PCI-to-DRAM cycle
• Supports PCI mechanism #1 only
• PCI spec. 2.1 support. [N(16/8)+8 rule, passive release, fair arbitration]
• Enhanced performance for memory-read-line, memory-read-multiple, and
memory-write-multiple
• Invalidates PCI commands
• DRAM refresh during 5V system suspend
• I/O leakage stopper for power saving during system suspend
• 328-pin or 388-pin BGA process