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3
Unused Pods...................................................................................................................................23
Offline Analysis .............................................................................................................................24
Filtering..........................................................................................................................................25
Timing Analysis Operation...................................................................................................26
Loading the Inverse Assembler and Decoding DDR Commands .............................................26
Taking a Trace, Triggering, and Seeing Measurement Results................................................26
State Analysis Operation.......................................................................................................26
Minimizing intermodule skew......................................................................................................26
The Inverse Assembler and Decoding DDR Commands...........................................................27
Taking a Trace, Triggering, and Seeing Measurement Results................................................27
Tracing the Serial Presence Detect Signals.........................................................................28
Using Eye Finder with the FS2331 DDR Probe..................................................................29
Using EyeScan with the FS2331 Probe ...............................................................................30
Using the FS2331 DDR Probe with an Interposer (FS1024/25) ................................................31
DIMM Signal Loading Option.....................................................................................................31
FS2331 Calibration .......................................................................................................................32
Step 1 – Set Command sample position..................................................................................................34
Step 2 – Write Burst Data Valid Position...............................................................................................37
Step 3 – Read Burst Data Valid Position ................................................................................................41
Step 4 – Adjust the delay line value to maximize R/W overlap ............................................................45
Step 5 – Set the final analyzer sample position ......................................................................................45
General Information.............................................................................................................47
Probe Interface design capability............................................................................................................47
Standards supported ................................................................................................................................47
Power requirements..................................................................................................................................47
Logic Analyzer Requirements .................................................................................................................47
Minimum Clock Period............................................................................................................................47
Signal Loading ..........................................................................................................................................47
Environmental Operating Limits............................................................................................................47
Servicing....................................................................................................................................................47
Signal Connections ...............................................................................................................48