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The MAC ASIC
OmniSwitch Troubleshooting Guide September 2005 page -7
Coronado: The “Brain” of the System
• Provides hardware performance for most features on the OmniSwitch.
• Involved in both the ingress and egress packet processing.
• Provides a high speed connection to Catalina via the XYBUS. XYBUS is two unidirectional busses
between Catalina and Coronado. XYBUS is 1.24 Gbps.
• Provides 2 high speed connections to the fabric via the FBUS. An FBUS is two unidirectional busses.
• Provides connections to all the ASICs via the management BUS known as BBUS. BBUS is a bidirec-
tional bus used for Management purposes for NI/CMM communications.
Coronado Specifications
• On Chip 170 KB memory (for FIFOs, Queue Manager and ingress buffering)
• Off Chip memory
• SSRAM: 2Mbytes for pseudoCAM entries (128k)
• 64k Layer 2 entries (32K for SA and 32K for DA)
• 64k Layer 3 entries
• SDRAM-0: 32Mbytes (Part of it is allocated to HW for HRE header cache, Priority Description Index
etc; remaining is available to Software)
• SDRAM-1: 16Mbytes used for the buffers
• V7 Sparc Core running at 143 MHz—integrates cache memory:
- 8KB for instruction
- 4KB for data (sending on BBUS)
- 2KB for packet cache (for faster access to the packet being processed)
• Provides software support for distributed features. Executes the Operating System on each NI. The
configuration of the Coronado is updated by the CMM.
• The Coronado ASIC supports 2048 queues and 4096 buffers. Buffers are organized in two lists:
- List 1: 4096-128=3968 buffers of 2048 bytes
- List 2: 128 buffers of 16384 bytes for Jumbo Frames
• Coronado keeps track of the buffer utilization on per port basis. A per port threshold triggers the
802.3x pause frame.
• Each queue can be assigned:
- An egress physical port or can be designated as a multicast queue
- A pay that determines the right to transmit a certain amount of data
- A priority (4 for unicast - 4 for multicast)
- A maximum length, which is the maximum number of packets that can be queued